Leading Edge Subsystem Timing Expert

4 days ago

Ellore, Andhra Pradesh, India beBeeSeniorTiming Full time ₹ 40,00,000 - ₹ 60,00,000
Senior Timing and Physical Design Engineer

We are seeking a seasoned Senior Timing and Physical Design Engineer to lead complex subsystems through robust timing closure and physical implementation.

  • Develop and refine methodologies for Static Timing Analysis (STA) and Place and Route (PNR), tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems.
  • Drive automation and validation of timing and physical design data across subsystem boundaries, ensuring seamless integration and efficient workflows.
  • Mentor junior engineers, fostering technical growth and knowledge sharing within subsystem teams, and collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.

Requirements:

  • 10+ years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below).
  • Demonstrated expertise in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus) and PNR tools (e.g., Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems.
  • Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
  • Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks.
  • Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems.
  • Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred.

Preferred Qualifications:

  • Background in high-speed interfaces or mixed-signal SoC subsystems.

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