High Performance Design Engineer

2 days ago

Hyderabad Secunderabad Telangana, India beBeePhysicalDesigner Full time ₹ 1,04,000 - ₹ 1,30,878

The job involves collaborating with an experienced physical design team to deliver tile and full-chip designs that meet the challenging goals for frequency, power, and other design requirements in a fast-paced environment.

The ideal candidate has significant industry experience, is eager to take on new challenges, and possesses excellent analytical and problem-solving skills. They have strong communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. The individual is meticulous about power, performance, and area while driving schedule and managing cost. They are adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around them.

Key Responsibilities
  • RTL to GDSII flow
  • Handling floor-planning, physical implementation of power-planning, synthesis, placement, CTS, routing, extraction, timing closure (tile level, full chip), physical verification (DRC LVS), crosstalk analysis, EM/IR
  • Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Identify and implement opportunities for improving PPA

Preferred Experience:

  • 16+ years of professional experience in physical design, preferably with high-performance designs.
  • Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications.
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
  • Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
  • Experience in STA, full-chip timing
  • Versatility with scripts to automate design flow. Proficiency in scripting languages, such as Perl and Tcl.
  • Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
  • Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm
  • Excellent physical design and timing background.
  • Good understanding of computer organization/architecture is preferred.
  • Strong analytical/problem-solving skills and pronounced attention to details.

Academic Credentials:

  • Qualification: Bachelors or Masters in Electronics/Electrical Engineering

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