Verification Test Engineer
4 days ago
We are seeking a skilled Verification Test Engineer to join our team in Hyderabad. The ideal candidate will have experience in designing and implementing System Verilog-based functional verification environments.
The successful candidate will be responsible for behavioral modeling of functional blocks, system-level performance verification, analyzing traffic patterns, bandwidth, and latency to ensure optimal system behavior.
A strong background in AXI4 bus protocol and Network On Chip (NOC) protocol is highly desirable. The selected candidate will work closely with our design team to develop and integrate verification environments.
The responsibilities of this role include setting up and configuring verification environments, creating drivers, monitors, scoreboards, test sequences, traffic patterns, and bringing up simulations.
Additionally, the selected candidate will be responsible for replacing RTL with SV behavioral models and performing RTL correlation through functional and performance regressions, debugging failures.
The ideal candidate will also analyze traffic patterns, bandwidth, and latencies to optimize system performance and rigorously test using multiple verilog simulators, including VCS, NCSIM, and Questa.
Benefits:
- Competitive salary ranging from $120,000 to $180,000 per annum.
- Opportunity to work with a leading Data Analytics company.
- Chance to develop innovative products and solutions.
- Collaborative and dynamic work environment.
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