
Technical Lead
3 days ago
We are seeking a highly skilled Technical Lead to spearhead our DFT efforts.
Key responsibilities include defining and driving DFT strategy and architecture for complex ASIC/SoC projects, implementing and verifying DFT features, managing the end-to-end DFT flow, collaborating with cross-functional teams, and performing pattern generation, fault simulation, and debug test coverage gaps.
This position requires a strong understanding of RTL design, STA, and synthesis flows, as well as expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. Proficiency in scripting languages (Python, Perl, Tcl) for flow automation is also necessary.
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design
- 7+ years of experience in DFT for complex ASIC or SoC designs
- Hands-on experience with DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, and Cadence/others: Modus, Encounter Test
- Opportunity to work on cutting-edge technology
- Collaborative and dynamic work environment
- Professional growth and development
Preferred Qualifications:
- Experience with hierarchical DFT and low-power DFT methodologies (UPF)
- Exposure to post-silicon validation and failure analysis
- Familiarity with safety-critical designs (ISO 26262) and functional safety
- Experience working in advanced nodes (e.g., 7nm, 5nm, FinFET)
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