Senior ASIC SOC Microarchitecture Engineer

2 days ago


Guntur, Andhra Pradesh, India beBeeRTL Full time ₹ 18,00,000 - ₹ 21,50,000

Job Overview

The ASIC SOC RTL Design Lead is responsible for defining and developing microarchitecture specifications for complex SoC designs. This role requires strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis.

Key Responsibilities:

  • Develop microarchitecture specifications for complex SoC designs.
  • Lead RTL design and implementation, ensuring optimal performance, power, and area (PPA).
  • Collaborate with system architects, verification teams, and physical design teams to ensure successful project execution.
  • Perform design trade-off analysis to meet functional, performance, and power requirements.
  • Develop and implement design methodologies to improve efficiency and quality.
  • Mentor and guide junior engineers, fostering a culture of innovation and excellence.
  • Participate in design reviews, provide technical leadership, and ensure adherence to project timelines.

Required Skills and Qualifications:

  • 8+ years of hands-on experience in RTL design and microarchitecture development.
  • Strong expertise in RTL design using Verilog/SystemVerilog and logic synthesis.
  • Proficiency in microarchitecture design for complex SoCs, including pipelining, caching, and memory subsystems.
  • Experience with low-power design techniques, such as clock gating and power gating.
  • Familiarity with advanced process nodes and their specific challenges.
  • Strong scripting skills in Tcl, Python, or Perl for automation and flow development.
  • Excellent problem-solving skills and attention to detail.
  • Strong communication and leadership skills.


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