
Senior Design Engineer Position Open
4 days ago
This role involves all aspects of physical design for full-chip and block-level designs. The responsibilities include floorplanning, placement, budgeting, clock tree planning and analysis, scan re-ordering, clock tree synthesis, placement optimization, routing, timing and SI analysis/closure, ECO tasks, EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.
">Key Responsibilities:- Develop and implement design automation using various EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools & flow.
- Collaborate with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
- Develop a strong understanding of timing constraints, SI prevention, and power reduction.
- Utilize Synopsys/Cadence/Mentor place and route tools for efficient design implementation.
- Proficient in Unix/TCL/Perl programming languages.
- Excellent communication and presentation skills, along with good interpersonal skills and problem-solving ability.
- Minimum 4+ years experience in ASIC physical design.
- Strong background in block implementation, extraction, timing, and full-chip designs.
- Effective communication and hands-on TCL/Perl development skills.
- Opportunity to work on complex chip projects.
- Chance to collaborate with experienced professionals in the field.
- Professional growth and development opportunities.
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