System-on-Chip and Intellectual Property Design Verification Engineer

2 weeks ago

Bengaluru, Karnataka, India beBeeVerification Full time US$ 1,50,000 - US$ 2,00,000
Job Title: Staff IP Design Verification CXL

The ideal candidate will be part of a leading edge R&D team responsible for the verification of complex system-on-chip (SoC) and intellectual property (IP) designs. The successful applicant will own and develop UVM based testbench environments, which handle multiple features of IP and SoC.

  • Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC.
  • Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc
  • Good knowledge of System Verilog.
  • Hands-on experience with coverage closure and writing SVA for IP/SOC.
  • Good simulation debugging skills.
  • Experience with Perforce or similar revision control environment.
  • Experience with Python/TCL or any scripting knowledge is an added advantage.

Responsibilities include:

  • Understand Standard Specifications, create test plan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification.
  • Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release
  • Perform peer review of testbench code for continuous quality.
  • Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure.
  • Periodically publish technical papers and/or file patents on the feature updates/innovation carried out.
  • The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
  • In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

The role requires a strong background in digital design verification and a deep understanding of UVM based testbench development. Experience with various design tools such as ModelSim, Questa, and VCS would be highly beneficial.

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