
Senior Design Verification Engineer
2 weeks ago
Exciting Opportunities in Univision Technology Pvt Ltd
Designation: Senior Verification Engineer
Notice Period: Immediate to 30 days
Roles and Responsibility:
Bachelor's/Master's degree in CS/EE/EC engineering
6-10 years of experience in driving functional verification for Intellectual Properties (IPs) and System-on-a-Chip (SoCs).
Hands on working experience with System Verilog and developing Universal Verification Methodology (UVM).
Knowledge of MIPI protocols and high speed SERDES or parallel interface
Deep technical expertise in different verification techniques & methodologies including formal, GLS, UPF based Power simulations etc
Familiar with serial protocols like SPI, I2C, MDIO, UART
Proficiency in scripting languages (Python) for automation and analysis
Interested candidates share your updated resume to gunashree.k@tarassolution.com
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