
Digital Systems Verification Specialist
3 days ago
We are seeking an experienced Design Verification Engineer to work on the design and verification of complex digital systems.
Responsibilities:
- Understand business requirements and functional specifications of IPs, subsystems, and SOC
- Create a Verification Environment Architecture document
- Review and revise designs to meet acceptance criteria
- Develop code in System Verilog, UVM, C for unit, subsystem, and SOC level verification
- Perform RTL simulations using Synopsys and Cadence simulators
- Debug and resolve problems found by simulations
- Develop performance test plans and maintain them
- Develop transactors, monitors, and models for performance verification
- Implement performance verification flow including monitoring, synchronization, reporting, and self-checking mechanisms
- Provide full reports of performance metrics and bottlenecks
- Track tickets and code releases using a Bug Tracking tool and GIT
- Perform UPF based Power Aware simulations
- Coding of Assertion and Functional Coverage bins in SVA
- Code and Functional Coverage Closure
- Perform Gate Level simulations
- Prepare and conduct reviews of Verification Sign-off documents to ensure SOC tape-out quality
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