
Senior Verification Specialist
1 day ago
We are seeking a Senior Verification Engineer to join our team. As a member of our engineering group, you will play a critical role in the design and verification of complex digital systems.
The ideal candidate will have a strong background in digital design and verification, with experience in developing and executing detailed verification plans for IP blocks, subsystems, or SoCs.
Key Responsibilities:- Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
- Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
- Write and maintain directed and constrained-random test cases.
- Perform Gate-Level Simulation (GLS) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
- Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
- Validate high-speed protocols (e.g., PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, CXL).
- Debug RTL and testbench issues using waveforms, logs, and assertions.
- Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
- Analyze functional/code/line/branch/coverage metrics and drive closure.
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- Expertise in SystemVerilog, UVM, and constrained-random verification.
- Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
- Strong debugging skills and understanding of design specs and verification architecture.
- Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
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