
Senior Verification Specialist
4 days ago
We are seeking a highly skilled Verification Engineer to join our team.
- Design Verification
- 3-5 years of experience in the field
Bangalore is the preferred location for this role.
The ideal candidate will have hands-on experience with GLS, ZD/PAGLS/SDF/Scan dump verification. Strong skills in Debug, UVM, System Verilog and Digital Fundamentals are also required.
A strong background in Netlist functional failure debugging and Low Power Awar verification is essential.
Timing Simulation failure, setup and hold violation fundamentals should be well understood.
Scan dump verification and understanding Specs and Standards are necessary.
Mastery of Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved is required.
Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5) and Bus protocols like AHB/AXI/ACE/ACE-Lite is necessary.
Please drop your updated resume to janagaradha.n@acldigital.com if you are interested in the position.
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