Digital Fault Tolerance Lead

2 days ago


India beBeeDigitalFaultTolerance Full time ₹ 23,04,000 - ₹ 2,59,20,000
Digital Fault Tolerance Engineer

We are seeking a skilled DFT engineer to lead the development and implementation of Digital Fault Tolerance methodologies.

Key Responsibilities:
  • Develop and implement DFT logic integration and verification.
  • Experience in debugging low coverage and Design Rule Checks fixes.
  • Gate Level ATPG simulation with and without timing.
  • Pattern generation, verification, and delivery to test teams.
  • Post silicon debug and support on failing patterns.
  • Good experience with tools from Synopsys like TestMAX.
  • Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process.
Requirements:
  • 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
  • Excellent problem-solving and debugging skills. Proactive in nature.
  • Leading junior teams, Mentoring/Training, and Project leadership.


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