Chief Digital Fault Tolerance Architect

2 days ago

India beBeeDft Full time ₹ 15,00,000 - ₹ 25,00,000
Job Title: Lead DFT Engineer

We are seeking a seasoned expert to lead the development of complex SoC/ASIC designs.

Key Responsibilities:

  • Develop and drive DFT strategy and architecture for multiple ASIC/SoC projects.
  • Implement and verify DFT features like scan insertion, ATPG pattern generation, MBIST, boundary scan, and IJTAG.
  • Manage end-to-end DFT flow from RTL to gate-level netlist and silicon bring-up.
  • Collaborate with cross-functional teams for seamless integration.
  • Perform pattern generation, fault simulation, and debug test coverage gaps.
  • Own DFT signoff, timing closure, and ATE pattern delivery.
  • Support silicon bring-up, test vector validation on ATE, and yield optimization.
  • Mentor junior engineers and develop DFT automation scripts and infrastructure.

Requirements:

  • Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
  • 7+ years of experience in DFT for complex ASIC or SoC designs.
  • Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
  • Hands-on experience with DFT tools such as Synopsys, Siemens EDA, and Cadence.
  • Strong knowledge of RTL design, STA, and synthesis flows.
  • Proficient in scripting languages (Python, Perl, Tcl) for flow automation.

What We Offer:

  • A competitive salary and benefits package.
  • Opportunities for professional growth and development.
  • A collaborative and dynamic work environment.

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