
Physical Design Expert
1 day ago
Tessolve is seeking an experienced Physical Design Engineer to join our team. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
Key Responsibilities:
- Lead the end-to-end physical design flow from RTL to GDSII at advanced technology nodes.
- Optimize chip area, power, and performance through floorplanning and partitioning.
- Place and route standard cells, buffers, and clocks using CTS and STA.
- Work on congestion analysis, RC extraction, and static timing analysis (STA).
- Implement low-power techniques such as clock gating, power gating, and multi-voltage domains.
- Perform DRC, LVS, and Antenna checks using industry-standard tools.
- Collaborate with other teams for design convergence and debug timing, power, and physical verification issues.
- 4 to 8 years of experience in Physical Design and Implementation.
- Strong knowledge of EDA tools including Synopsys ICC2/Fusion Compiler, Cadence Innovus, or Mentor Olympus.
- Experience in floorplanning, power planning, placement, routing, and timing closure.
- Expertise in Static Timing Analysis (STA) using Primetime or Tempus.
- Hands-on experience in physical verification tools including Calibre, PVS, or Pegasus.
- Good understanding of design constraints, clock tree optimization, IR drop, and power integrity.
- Opportunity to work on cutting-edge semiconductor technology.
- Exposure to advanced process nodes and complex designs.
- Collaborative and innovative work environment.
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