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1 day ago
We are seeking an experienced Senior Physical Design Engineer to create and implement top-level floor plans, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs) in addition to SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
The ideal candidate will have extensive experience with 65nm or lower node designs, utilizing advanced low power techniques such as Voltage Islands, Power Gating, and substrate-bias. Additionally, the successful candidate will provide technical guidance and mentoring to physical design engineers, interface with front-end ASIC teams to resolve issues, and possess excellent communication skills.
A strong background in ASIC physical design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, and expertise in Cadence or Synopsys or Magma physical design tools is essential. The ability to script using PERL, TCL, and a solid Physical Verification skill set are also necessary.
As a Senior Physical Design Engineer, you will work on a wide range of projects from Consumer Electronics to Networking & Telecommunications, and must be able to interface with different teams and prioritize work based on project needs.
- Experience with advanced low power techniques: Voltage Islands, Power Gating, and substrate-bias
- Expertise in Cadence, Synopsys, or Magma physical design tools
- Strong scripting skills in PERL and TCL
- Solid Physical Verification skill set
This role offers the opportunity to work on innovative semiconductor solutions and collaborate with diverse teams to deliver high-quality results.
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