Senior DFT Engineer Position

13 hours ago

Thāne, Maharashtra, India beBeeDft Full time ₹ 15,00,000 - ₹ 25,00,000

Job Overview

We are seeking a highly skilled and experienced DFT (Design for Testability) engineer to fill this key role.

Key Responsibilities:

  • Develop in-depth knowledge of DFT concepts and techniques, including designing and implementing test strategies for complex digital circuits.
  • Expertise in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis is essential.
  • A strong understanding of test mode timing constraints definition and the ability to provide corrective actions for timing violations is also required.
  • Familiarity with scripting languages such as Perl and shell is necessary.
  • Experience in RTL and gate-level simulations of scan and MBIST test vectors is preferred.
  • A working knowledge of equivalence check, DFT DRC rules, both in RTL lint tools like Spyglass and ATPG tools like TetraMax, is advantageous.
  • Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus.
  • The successful candidate will have excellent problem-solving skills, the ability to work in an international team environment, and adapt to new tools and methodologies quickly.
  • Strong communication and teamwork skills, along with good English language proficiency, are essential.

About the Role

This position involves designing and implementing test strategies for complex digital circuits. The ideal candidate will have a strong understanding of DFT concepts and techniques, as well as expertise in test mode timing constraints definition and corrective actions for timing violations.

Requirements

To be successful in this role, you will need to have the following skills and qualifications:

  • In-depth knowledge of DFT concepts and techniques.
  • Expertise in scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
  • Strong understanding of test mode timing constraints definition and corrective actions for timing violations.
  • Familiarity with scripting languages such as Perl and shell.
  • Experience in RTL and gate-level simulations of scan and MBIST test vectors.
  • Working knowledge of equivalence check, DFT DRC rules, both in RTL lint tools like Spyglass and ATPG tools like TetraMax.
  • Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test.
  • Excellent problem-solving skills.
  • Ability to work in an international team environment.
  • Adaptability to new tools and methodologies.
  • Strong communication and teamwork skills.
  • Good English language proficiency.

What We Offer

This role offers a challenging and rewarding opportunity to work on complex digital circuit design and testing. You will have the chance to develop your skills and expertise in a dynamic and international team environment.

Contact Information

Please note that company information has been removed from this description.

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