Senior RTL Design Engineer
3 weeks ago
We are developing cutting-edge 5G ready wireless systems to address rural and urban high bandwidth networking requirements. We are looking for a strongly motivated candidate with hands-on experience in System Verilog programming for wireless baseband design.
Key Responsibilities:
- Participate in architecture definition, implementation, and test plan development.
- Develop and implement RTL level blocks, perform synthesis, implement on FPGAs, and resolve timing violations.
- Coordinate with the Software and Hardware team to identify system issues and resolve them.
Requirements:
- 5+ years of work experience and 2+ years of experience in handling a team.
- Strong base in digital design, RTL, and FPGA development flows.
- Proficiency in HDLs like SystemVerilog/Verilog for RTL Design.
- Knowledge and experience of building IPs using AXI4, AXI4 Lite, and AXI4 Stream Protocol.
- Basic understanding in Xilinx FPGA Architecture and tools like Vivado.
- Good understanding in digital signal processing techniques such as Fast Fourier Transform, and good handle on linear algebra and complex algebra is a plus.
- Good understanding in realization of baseband for wireless systems such as OFDM is a plus.
- Ability to research unfamiliar technologies and methods for application in our product development and support.
- Ability to understand and follow engineering processes such as JIRA and version control (Git).
Benefits:
- We offer great career growth, ESOPs, Gratuity, PF, and Health Insurance.
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