Senior ASIC Design Expert

4 days ago

Bengaluru, Karnataka, India beBeeEngineer Full time ₹ 15,00,000 - ₹ 28,00,000
Job Overview

As a skilled ASIC Engineer 3, you will play a key role in leading and implementing physical designs of complex ASICs. With good understanding of the physical design flow from RTL to GDS, you will work closely with internal Design teams and Methodology teams to successfully tape out multiple blocks of complex ASICs on advanced process nodes.

Key Responsibilities
  • Manage all aspects of Physical Design for Full-chip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis fixes, Low Power solution development implementation.
  • Utilize sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools flow, etc.
  • Collaborate with the methodology team to solve implementation challenges and provide inputs to improve the Physical design flow.
  • Experience in design automation is required.
  • Understanding of Timing constraints, SI prevention, Power reduction is necessary.
  • Prior experience with Synopsys/Cadence/Mentor place and route tools is mandatory.
  • Ability to complete design in 16nm and or 7nm is essential.
  • Proficiency in Unix/TCL/Perl is required.
  • Good communication and presentation skills are necessary. Good interpersonal skills and problem-solving ability are also required.
Requirements
  • 4+ years experience in ASIC physical design is necessary.
  • Experience with block implementation, extraction, timing and or full-chip designs is required.
  • Strong communication skills are necessary.
  • Strong hands-on TCL/Perl development skills are required.
Preferred Qualifications
  • Experience as a full-chip floor planning, routing, or timing lead for a large silicon project is preferred.
  • Track record of taping out complex chips on advanced process nodes is desired.

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