Senior Verification Specialist

2 weeks ago


Alwar, Rajasthan, India beBeeVerification Full time ₹ 1,00,00,000 - ₹ 1,80,00,000

Job Overview:

  • We are seeking a skilled and experienced Design Verification Engineer to join our team.
  • The ideal candidate will have expertise in SystemVerilog, UVM, and constrained-random verification, with strong debugging skills and understanding of design specs and verification architecture.
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering is required, along with 5–15 years of experience in ASIC/IP/SoC/Processor Design Verification.

Key Responsibilities:

  • Developing and executing detailed verification plans for IP blocks, subsystems, or SoCs.
  • Designing and building SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  • Writing and maintaining directed and constrained-random test cases, performing GLS (Gate-Level Simulation), and verifying processor cores or custom pipelines.
  • Validating high-speed protocols, debugging RTL and testbench issues, and collaborating with cross-functional teams to drive quality and coverage closure.

Requirements and Qualifications:

  • Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
  • Minimum 5-15 years of experience in Design Verification.
  • Expertise in SystemVerilog, UVM, and constrained-random verification.
  • Familiarity with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
  • Strong debugging skills and understanding of design specs and verification architecture.


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