
Senior Verification Engineer
5 hours ago
Key Responsibilities:
- Strategic Leadership: Develop and execute verification strategies for analog/mixed-signal IPs and SoCs to ensure timely delivery and quality standards.
- Verification Planning: Define and implement verification plans, including testbenches, stimulus generation, and checking strategies to validate design functionality.
- Environment Development: Create and maintain SystemVerilog, Verilog-AMS, or UVM-based verification environments, performing co-simulation of analog/digital designs using industry tools like Cadence, Synopsys, and Siemens EDA.
- Simulation and Debugging: Conduct mixed-signal simulations, behavioral modeling of analog blocks, and integration into top-level environments, debugging complex AMS simulation issues across multiple abstraction levels.
- Coverage Analysis: Drive coverage analysis and sign-off using functional, formal, and assertion-based methods, ensuring comprehensive verification.
Required Skills:
- At least 8 years of hands-on experience in analog/mixed-signal verification with a proven track record in building verification environments using SystemVerilog, Verilog-AMS, or UVM.
- Strong background in mixed-signal simulation and behavioral modeling, with expertise in creating AMS behavioral models (e.g., Verilog-A/AMS) for early integration and verification.
Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, with a strong foundation in digital and analog electronics, computer architecture, and software engineering principles.
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