High-Performance ASIC Design Expert
3 days ago
We are seeking a skilled professional to fill the role of Senior ASIC Design Engineer. The ideal candidate will have extensive experience in physical design and a strong background in developing high-performance designs.
The successful candidate will be responsible for leading the physical design efforts for next-generation ASICs, working closely with customers, SOC architects, the CAD team, and the design team.
- Implementing RTL to GDS2 flow for complex digital circuits
- Expertise in floor-planning, power-plan implementation, synthesis, placement, timing closure, routing, extraction, DRC/LVS, crosstalk analysis, EM/IR, and formal equivalence verification
- Proficient in using PNR tools including Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus
The ideal candidate will have 12+ years of professional experience in physical design, preferably with high-performance designs. Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications is also required.
A strong understanding of computer organization/architecture is preferred, as well as excellent physical design and timing background. Strong analytical/problem-solving skills and attention to detail are essential.
Bachelor's or Master's degree in Electrical Engineering or Computer Science is required. 10 years of experience in physical design roles leading to an understanding of RTL to GDS development is preferred.
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