
Senior/ Lead ASIC RTL Design engineer
4 weeks ago
Work Location: Bangalore/ Hyderabad/ Ahmedabad
Job Responsibilities
- Define micro-architecture and write detailed design specifications.
- Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog.
- Implement complex digital functions and algorithms in RTL.
- Create and execute detailed test plans to verify RTL designs.
- Optimize designs for power, performance, and area (PPA) constraints.
- Proficiency in writing and debugging RTL code.
- Experience with synthesis, static timing analysis, and linting tools.
- Familiarity with scripting languages such as Python, Perl, or TCL for automation.
- Experience in any of processor subsystem design, interconnect design, high speed IO interface design.
Eteros Technologies, Inc. is a Semiconductor Engineering services startup, Founded in 2020 in Silicon Valley and led by professionals with over 150 years of combined semiconductor design experience, the Eteros team has numerous successful tape outs under its belt and a global presence of customers spanning the US, Europe and APAC.
We work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Kindly visit (https://www.eterostech.com/) for more details.
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