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DFT Architect for Advanced SoC Designs
2 weeks ago
Key Responsibilities
- Interfacing with design teams to ensure DFT design rules and guidelines are met
- Interacting with PD and Front End Integration teams for Scan Insertion
- Generating high-quality manufacturing test patterns for stuck-at, transition fault models, and CA model
- Simulating and verifying ATPG and LBIST patterns
- Working with product engineering teams on the delivery of manufacturing test patterns
- Developing, enhancing, and maintaining scripts as necessary
- Able to technically guide and mentor junior folks in the team
PREFERRED EXPERIENCE:
- Experience in creating and implementing complex chip-level DFT architecture
- Proficient in logic design using Verilog
- Experience in DFT implementation including Scan insertion, ATPG, and Simulations
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
- Experience in debugging low coverage and DRC fixes
- Experience of debugging test pattern issues
- Support the Silicon bringup activities to guarantee highest stability of the test pattern
- Knowledge of MBIST is a plus
- Knowledge of synthesis is a plus
- Experience with post-silicon debug
- Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
- Any Tessent Scan/ATPG certifications is a plus
- Excellent presentation and inter-communication skills
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
- Prior experience as DFT engineer
