
Leading Edge Chip Design
5 days ago
Senior Design Engineer & Timing Closure Expert
Lead the synthesis, static timing, and DFT efforts for an advanced mixed signal chip as a Staff Design Engineer/Design Manager. This highly visible role is part of a talented team at the heart of Soc design effort.
As a Sr ASIC STA Engineer, you will provide integrated solutions in a growth industry, utilizing expertise in STA tools and methodologies for timing closure.
Key Responsibilities:
- Full chip and block level timing closure ownership throughout the project cycle (RTL, synthesis, and physical implementation)
- Develop and maintain methodology and flows related to timing verification and closure
- Generation of block and full chip timing constraints
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid ECO timing closure
- Support digital chip integration work and flows
Requirements:
- B.Tech/M.Tech/Ph.D. with 6+ years experience in ASIC timing constraints generation and timing closure
- Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with good understanding of OCV, noise, and crosstalk effects on timing
- Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes
- Knowledge of timing corners/modes and process variations
- Knowledge of low-power techniques including clock gating, power gating, and millivoltage designs
- Proficient in scripting languages (Tcl and Perl)
What's in it for you:
- Work on leading edge technologies
- Career development and growth opportunity
- Competitive compensation
- Medical benefits
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