Synthesis and Performance Optimization Specialist

3 days ago

Rajahmundry, Andhra Pradesh, India beBeeTiming Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

Job Title:

Synthesis and Static Timing Analysis Engineer


Job Description:

Lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip. Develop and maintain methodology and flows related to timing verification and closure.


Responsibilities Include:

  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
  • Generation of block and full chip timing constraints.
  • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
  • Support digital chip integration work and flows.


Key Qualifications:

  • Btech/Mtech/Phd with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure.
  • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.
  • Knowledge of timing corners/modes and process variations.
  • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).
  • ECO timing flow
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).
  • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.
  • Must be able to solve complex problems and independently drive tasks to completion in a timely manner.
  • Be able to work under limited supervision and take complete accountability.

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