High-Performance ASIC Physical Design Expert

1 week ago

Bengaluru, Karnataka, India beBeePhysicalDesignEngineer Full time ₹ 1,04,000 - ₹ 1,30,878
Job Title

We are seeking a highly skilled Physical Design Engineer to lead our ASIC Physical Design team. As a key member of the design team, you will be responsible for implementing and delivering high-performance designs from RTL to GDS2.

Responsibilities
  • Implementing the RTL to GDS2 flow, ensuring timely delivery of designs and meeting project requirements.
  • Handling floor-plan, physical implementation of power-plan, synthesis, placement, CTS, timing closure, routing, extraction, physical verification (DRC LVS), crosstalk analysis, EM/IR, and formal equivalence.
  • Proficient in handling different PNR tools, including Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, and Innovus.
  • Full chip level floor planning, bus/pin planning, feed-thru planning, clock tree synthesis, placement, optimization, routing, parasitic extraction, static timing analysis, physical verification, and sign-off tasks.
  • Identifying complex technical problems, breaking them down, summarizing multiple possible solutions, and driving hands-on flow development and scripting.
Preferred Experience
  • 14 years of professional experience in physical design, preferably with high-performance designs.
  • Experience in automated synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic applications.
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
  • Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.
  • Versatility with scripts to automate design flow.
  • Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams.
  • Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm.
  • Excellent physical design and timing background.
  • Good understanding of computer organization/architecture is preferred.
  • Strong analytical/problem-solving skills and pronounced attention to details.
Academic Credentials
  • BS or MS degree in Electrical Engineering or Computer Science. 10 years of experience in physical design role leading to an understanding of RTL to GDS development.

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