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Staff Design Verification Engineer

1 month ago

Bengaluru, Karnataka, India Tenstorrent Full time
About Tenstorrent

Tenstorrent is a leading innovator in cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. Our team of technologists has developed a high-performance RISC-V CPU from scratch, and we're passionate about building the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems.

Job Summary

We're seeking an experienced engineer with a strong background in L2/Shared Cache verification to join our team. As a Verification Engineer, you'll contribute to the functional and performance verification of a server-class L2/Shared Cache unit from scratch, collaborating closely with Architecture and RTL teams.

Responsibilities
  • Develop detailed verification plans for the L2/Shared Cache unit, including architectural (RISCV ISA) and microarchitectural functionality
  • Design and develop reusable block-level testbench components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers
  • Develop random and directed stimulus that spans pre-silicon, emulation, and post-silicon domains
  • Evaluate and integrate open-source toolchains into the DV flow
  • Develop a DV environment, tools, and infrastructure to enable functional verification for pre-silicon, emulation, and post-silicon
  • Work with design, test, and post-silicon validation teams to ensure high-quality delivery of the L2/Shared Cache block
Requirements
  • BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
  • Strong background and experience with high-performance OOO CPU microarchitecture, especially with load/store, caches, and memory subsystems
  • Experience working on x86, ARM, or RISCV-based CPUs
  • Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency, multi-processors, and fabric topologies
  • Significant experience debugging RTL and DV in a simulation environment
  • Verification methodologies and techniques – simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
  • Experience with C++/SV/UVM as well as scripting languages
  • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
  • Strong problem-solving and debug skills across various levels of design hierarchies
Compensation and Benefits

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.