Chief Memory Architect
1 week ago
We are seeking a highly skilled Memory Design Engineer to join our team. As a Senior Memory Design Engineer, you will be responsible for designing and developing memory compilers and Fast Cache instances for next-generation Cores. Your expertise in computer architecture, CMOS Transistors, and clocking schemes will enable us to achieve outstanding Performance, Power, and Area (PPA).
Your role will involve collaborating with our team members to balance Power versus Performance versus Area trade-offs in typical CMOS design. You will also be responsible for circuit simulation and optimization of standard cells.
To succeed in this role, you will require a minimum of 2 years of experience in SRAM/memory design, margin, char, and quality checks. Basic knowledge of scripting languages, such as Perl, TCL, or Python, is essential. Experience working on Cadence or Synopsys flows is also desirable.
Key Responsibilities- Develop memory compilers and Fast Cache instances for next-generation Cores
- Design high-speed/low-power CMOS circuits and clocking schemes
- Balance Power versus Performance versus Area trade-offs in typical CMOS design
- Circuit simulation and optimization of standard cells
- Minimum 2 years of experience in SRAM/memory design, margin, char, and quality checks
- Basic knowledge of scripting languages (e.g., Perl, TCL, Python)
- Experience working on Cadence or Synopsys flows
- Circuit simulation and optimization of standard cells
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