Synthesis and Chip Design Lead
3 days ago
Senior ASIC Static Timing Analysis Engineer
">Job Description:
We are seeking a skilled Senior ASIC Static Timing Analysis (STA) Engineer to join our SOC digital design team. As a key member of this team, you will be responsible for providing integrated solutions in the growth industry. You will lead the synthesis, static timing, and DFT efforts for an advanced mixed-signal chip.
You will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to customers quickly.
Responsibilities Include:
- Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
- Develop and maintain methodology and flows related to timing verification and closure.
- Generation of block and full chip timing constraints.
- Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.
- Support digital chip integration work and flows.
Required Skills and Qualifications:
The position requires thorough knowledge of the ASIC design timing closure flow and methodology. You must have expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise, and crosstalk effects on timing.
You should have familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm. Knowledge of timing corners/modes and process variations is also required.
In addition, you should have knowledge of low-power techniques including clock gating, power gating, and millivoltage designs. Proficiency in scripting languages (Tcl and Perl) is essential.
Benefits:
This role offers an opportunity to work on leading-edge technologies, career development, and growth. You will receive competitive compensation and medical benefits.
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