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4 days ago
We are seeking a seasoned engineer to lead our Static Timing Analysis and Place and Route activities for complex subsystems. This is a unique opportunity to work on the cutting-edge of system design.
- The ideal candidate will have experience with STA tools, such as Synopsys PrimeTime and Cadence Tempus, and PNR tools like Synopsys ICC2 and Cadence Innovus.
- They will have a proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems.
- A deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams is essential.
- Lead STA and PNR activities for complex subsystems ensuring robust timing closure and physical implementation.
- Develop methodologies for STA and PNR tailored to large, multi-interface or mixed-signal subsystems.
- Drive automation and validation of timing and physical design data across subsystem boundaries.
- Mentor junior engineers and foster technical growth and knowledge sharing within subsystem teams.
- Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration.
- 10+ years of experience in Static Timing Analysis and Place and Route for complex subsystems.
- Demonstrated expertise in STA and PNR tools applied to large, multi-block or hierarchical subsystems.
- Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification.
- Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows.
- Deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams.
- Opportunity to work on complex systems with cutting-edge technology.
- Collaborative environment with experienced professionals.
- Professional development and growth opportunities.
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