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Leading Timing Closure Specialist
2 weeks ago
This role involves leading the timing closure process for complex ASIC designs. The ideal candidate will have in-depth knowledge of timing closure methodologies and be well-versed in pre/post-layout constraint development.
- Key Responsibilities
- Design Team Collaboration: Work closely with the design team to develop functional and DFT constraints, ensuring that the design meets the required timing specifications.
- IP Level Constraint Integration: Integrate IP-level constraints into the design, taking into account the complexities of multi-voltage and switching-aware corners.
- Automation Skills: Possess good automation skills in PERL, TCL, and EDA tool-specific scripting, as well as expertise in abstraction techniques like Hyperscale/ILM/ETM.
- Detailed Knowledge: Have detailed knowledge of EDA tools and flows, particularly Tempus/Primetime, and experience with RC balancing and scaling analysis of full chip clocks and critical data paths.
Qualifications
- Education: BE/BTECH/MTECH in EE/ECE with proven experience in ASIC Physical Design.
- Experience: 7+ years of experience in the field, with a strong understanding of EDA tools and flows.
