
Digital Verification Specialist
3 days ago
We are seeking a skilled verification engineer to drive the development of digital verification strategies for cutting-edge technology.
The ideal candidate will possess a strong background in electrical or computer engineering and a minimum of 4 years of experience in digital verification, with a focus on gate-level simulation.
Key Responsibilities:
- Develop digital verification plans for complex electronic systems
- Maintain Verilog/SystemVerilog testbenches using SDF concepts
- Collaborate with cross-functional teams to integrate verification results into the design flow
- Utilize EDA tools such as Synopsys VCS, Cadence Xcelium, and Mentor Questa to optimize verification processes
Requirements:
- Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or equivalent
- 4+ years of experience in digital verification, with a focus on gate-level simulation
- Strong knowledge of Verilog/SystemVerilog and SDF concepts
- Familiarity with EDA tools and scripting languages (Perl/Python/TCL/Shell)
- Excellent debugging and problem-solving skills
- Good communication and teamwork abilities
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