Advanced Verification Specialist

2 weeks ago

Jamnagar, Gujarat, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Role Summary

We are seeking an experienced Design Verification Engineer to play a key role in the quality and functionality of our advanced ASICs and SoCs. This position requires strong technical expertise, excellent analytical skills, and the ability to collaborate effectively with cross-functional teams.

Job Description

The successful candidate will develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) to ensure exceptional code coverage. They will design and create high-quality verification environments (testbenches) to achieve thorough RTL functionality verification. In addition, they will utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality, debug and analyze verification failures, and lead and mentor junior DV engineers within the team.

Key Responsibilities:

  • Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
  • Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage
  • Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
  • Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
  • Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
  • Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
  • Participate in code reviews and champion best practices for verification code quality

Requirements:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
  • 7-10 years of solid experience in Design Verification for ASICs or SoCs
  • In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
  • Proven ability to develop, debug, and optimize complex verification environments
  • Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
  • Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
  • Experience with formal verification tools and techniques is a plus
  • Excellent analytical and problem-solving skills with a meticulous attention to detail
  • Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

Senior-Level Requirements:

  • Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
  • Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs
  • Proven track record of successfully leading and executing verification projects
  • In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices
  • Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques
  • Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages)
  • Excellent leadership, communication, collaboration, and problem-solving skills
  • Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines

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