
Verification Engineer Leader
1 day ago
Verification Engineering Leader
- Leads and contributes to the verification of complex IP blocks or SoC subsystems, developing test plans, verification strategies, and coverage metrics based on design specifications.
Key responsibilities include:
- Developing and maintaining constrained-random and directed testbenches using SystemVerilog/UVM, collaborating with architects, designers, and other verification engineers to identify and debug design issues.
- Maintaining verification infrastructure, scripts, and regression systems, performing functional and code coverage analysis, driving closure.
- Providing technical guidance and mentorship to junior team members, participating in silicon bring-up and post-silicon validation when needed.
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- 8–14 years of hands-on experience in ASIC/SoC verification, with strong expertise in SystemVerilog, UVM, and RTL simulation tools.
- Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
A challenging role in a dynamic environment with opportunities for growth and development. The ideal candidate will be a motivated professional with a passion for innovation and excellence.
CareerAdvancement',
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