Principal Verification Engineer

23 hours ago

Amrāvati, Maharashtra, India beBeeVerification Full time ₹ 2,00,00,000 - ₹ 2,50,00,000

Design Verification Engineer Role Overview

We are seeking an experienced Design Verification Engineer to fill a critical position in our organization.

The ideal candidate will have a strong background in design verification and a passion for delivering high-quality solutions that meet or exceed customer expectations.

Key Responsibilities:

  • Develop and implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
  • Assist with developing test-plans, debugging failures and analyzing coverage information to ensure successful project completion.
  • Create complex test benches in System Verilog using OVM/UVM methodology to verify the functionality of electronic designs.
  • Demonstrate hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol implementation.
  • Analyze low power simulation results and debug failures to ensure optimal system performance.
  • Apply scripting languages like Perl, Unix shell or similar languages to automate tasks and improve efficiency.
  • Maintain excellent written and oral communication skills to effectively collaborate with cross-functional teams.

Required Skills and Qualifications:

  • At least 8 years of experience in design verification engineering.
  • A Master's degree (or higher) in Electrical Engineering (EE), Computer Engineering (EC), or related field.
  • Excellent knowledge of computer architecture and design verification fundamentals, including System Verilog assertions and testbench methodologies.

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