Senior Verification Specialist

Job Title: Senior Design Verification EngineerLocation: Bengaluru, IndiaExperience: 5+ YearsNotice Period: Less than 30 DaysWe are seeking a senior verification specialist with expertise in SystemVerilog and UVM methodology for SoC/IP level verification. Strong knowledge of AXI/APB bus protocols and high-speed interfaces like USB, Ethernet, and DDR is highly...

Senior Verification Specialist RoleThe position of Senior Verification Specialist involves ensuring the quality and functionality of advanced ASICs and SoCs. It requires a strong foundation in verification methodologies, with expertise in industry-leading tools and techniques.Responsibilities:Develop comprehensive verification plans, utilizing leading-edge...

Design Verification SpecialistThis role involves overseeing the architecture of a verification environment from scratch.Key Responsibilities:Architecting DV methodology, flow development, test plan creation and executionPerforming chip verification in cooperation with design, architecture, system validation and software teamsDeveloping DV testing plans,...

### Job Description: ASIC Design Verification Engineer**Location:** - Bangalore, Chennai, Hyderabad, Noida,Malaysia, Germany.**Experience Range:** 5 to 20+ years**Key Responsibilities:**- Develop and execute test plans to verify complex ASIC designs.- Utilize System Verilog (SV) and UVM methodologies for verification tasks.- Perform functional, formal, GLS...

Senior Design Verification EngineerWe are seeking a skilled Senior Design Verification Engineer to join our team. As a Senior Design Verification Engineer, you will be responsible for leading the development and implementation of verification strategies and techniques to ensure the quality and reliability of complex semiconductor designs.About the Role:Lead...

Key ResponsibilitiesDesign Verification: 3-5 years of experience in ZD/PAGLS/SDF/Scan dump verification with strong Debug, UVM, System Verilog and Digital Fundamentals.Debug Netlist functional failure and Low Power Aware verification.Timing Simulation failure, setup and hold violation fundamentals and Scan dump verification.Understanding Specs and Standards...

Technical Expertise:Pre-silicon verification of complex IPs or SoCsAbout the Role:Lead and contribute to the verification of complex IP blocks or SoC subsystems.Develop test plans, verification strategies, and coverage metrics based on design specifications.Create and maintain constrained-random and directed testbenches using SystemVerilog/UVM.Collaborate...

Design Verification SpecialistWe seek an expert with a strong background in formal-based verification, regression, and debugging failures independently.8-10+ years of experience in SV/UVM/Specman.Proven expertise in functional and code coverage analysis, with a knack for handling sub-module-level verification.Effective written and verbal communication skills...

Job Title: Design Verification EngineerThis is a technical role where you will be responsible for the verification environment of new silicon projects. The right candidate will have hands-on experience with UVM and Verilog.Responsible for all aspects of verification methodology employed and for ensuring the application of uniform standards and adoption of...

We are seeking an experienced Design Verification Engineer to lead our verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.Job Responsibilities:Develop detailed verification plans for IP blocks, subsystems, or SoCs.Create SystemVerilog/UVM-based testbenches, scoreboards, monitors, and...