Senior Verification Architect

2 weeks ago

Davangere, Karnataka, India beBeeDesignVerification Full time ₹ 15,00,000 - ₹ 20,10,000

We are seeking an experienced Design Verification Engineer to lead our verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.

Job Responsibilities:
  • Develop detailed verification plans for IP blocks, subsystems, or SoCs.
  • Create SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
  • Write and maintain directed and constrained-random test cases.
  • Perform Gate-Level Simulation with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
  • Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
  • Validate high-speed protocols (e.g., PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, CXL).
  • Debug RTL and testbench issues using waveforms, logs, and assertions.
  • Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
  • Analyze functional/code/line/branch/coverage metrics and drive closure.
  • Automate regressions and result analysis using scripting languages (Python, Perl, Shell, Tcl).
Requirements:
  • B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
  • 5–15 years of experience in ASIC/IP/SoC/Processor Design Verification.
  • Expertise in SystemVerilog, UVM, and constrained-random verification.
  • Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
  • Proven track record in one or more of the following areas:
  • Processor/Microarchitecture Verification
  • High-speed Protocol Verification
  • Gate-Level Simulation Verification
About Us:

We offer a dynamic work environment with opportunities for growth and professional development. If you have a passion for design verification and want to join a team of experts in the field, we encourage you to apply.

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