Design Verification Engineer
1 month ago
Job Title: Design Verification Engineer
Job Summary:
We are seeking a highly skilled Design Verification Engineer to join our team at Analog Devices. As a key member of our verification team, you will be responsible for the end-to-end verification of complex microprocessor designs, neural nets, and high-speed peripherals.
Key Responsibilities:
- Develop and implement UVM testbench architectures and DV flows
- Define test plans, tests, and verification methodologies for block/subsystem and chip-level verification
- Work with the design team to generate and review test plans and closure of code and functional coverage
- Collaborate with other verification team disciplines to determine correct functionality
- Perform formal verification of IPs and subsystems
- Verify NOC, interconnect, and performance of complex SOCs
- Develop system-level use case scenarios and innovate verification solutions
Requirements:
- B.Tech/M.Tech with 2+ years of industry experience in digital pre-silicon verification
- Good understanding of SOC/subsystem design concepts and design architectures
- Hands-on experience in developing, updating, and debugging Verilog, SV-UVM, and SOC-level testbenches
- Experience in closing verification of block/subsystem level verification using industry-standard metrics
- Expertise in NOC, bus, and interconnect verification, coverage analysis, and improvements
- Strong knowledge of test-plan generation, coverage analysis, transaction-level modeling, pseudo, and constrained random techniques with System Verilog
- In-depth knowledge of SV-UVM and debugging of testbenches
- Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica, Neural Network, GPU Cores is a plus
- System Verilog, C/C++, System C, TCL/Python/shell-scripting
- Exceptional interpersonal and communication skills
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