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Digital Test Expert

2 weeks ago

Bengaluru, Karnataka, India beBeeDft Full time ₹ 20,00,000 - ₹ 23,00,000
About this Opportunity

This is a challenging position for an experienced Design for Testability (DFT) Engineer who can effectively develop and implement test compression and decompression scan methodologies to generate test patterns at block and SoC levels.

The ideal candidate will have a strong background in Scan design, Clock architecture, ATPG methodology, and industry-standard tools. They will be responsible for working on ATPG test pattern generation stuck-at and at-speed with depth fault coverage analysis to identify issues and meet coverage targets.

The role also involves designing and implementing boundary scan test plans and test coverage using JTAG standards, understanding and applying MBIST concepts and insertion, as well as test integration at partition and SoC levels.

Additionally, the candidate will develop knowledge of memory redundancy logic and its application in digital designs, stay up-to-date with JTAG concepts and IEEE standards, and work with industry-standard DFT tools.

Key Responsibilities:
  • Develop and implement effective test compression and decompression scan methodologies.
  • Work on ATPG test pattern generation stuck-at and at-speed with depth fault coverage analysis.
  • Design and implement boundary scan test plans and test coverage using JTAG standards.
  • Understand and apply MBIST concepts and insertion, as well as test integration at partition and SoC levels.
  • Develop knowledge of memory redundancy logic and its application in digital designs.
  • Stay up-to-date with JTAG concepts and IEEE standards.
Requirements:
  • 8+ years of experience in DFT engineering.
  • Strong understanding of Scan design, Clock architecture, ATPG methodology, and industry-standard tools.
  • Excellent knowledge of scripting languages such as TCL/Perl/Python.