Digital Design Verification Lead

5 days ago

Bengaluru, Karnataka, India Analog Devices Full time

Analog Devices is seeking a skilled Digital Design Verification Lead to join our Central Digital IP team. In this role, you will be responsible for providing technical leadership to the DV team, managing IP development and delivery, and interacting with internal customers to communicate, identify, improve, and maintain developed IP.

As a Digital Design Verification Lead, you will be responsible for verifying complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB, etc. using leading edge methodologies like UVM & Formal DV. You will create verification strategies and influence the decisions on methodologies to be adopted for the verification at block and sub-system level.

Key responsibilities include:

  • Verification of complex designs using UVM and Formal DV methodologies
  • Creation of verification strategies and influence on methodology adoption
  • Architecture of testbench and development of verification environment in UVM and Formal based verification approaches
  • Definition of testplan, tests and verification methodology for block / sub-system level verification
  • Integration of block testbench at sub-system level UVM environment and verification of integration
  • Packaging of verification environment for Digital IP for seamless integration into verification flow at different stages of execution
  • Technical mentoring and leading a team of verification engineers
  • Conducting detail-oriented DV reviews and driving adherence to quality metrics
  • Evaluation of 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and making recommendations

Requirements include a minimum B.E./ B.Tech/ M.Tech degree in Electrical/Electronics/Computer science, 10+ years of experience in design verification with UVM and constrained random, coverage based verification approaches, strong understanding of DV concepts with an eye on developing scalable DV environment architecture, and experience with translating Design Verification (DV) requirements into a robust DV environment and generating coverage metrics for demonstrating DV convergence.

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