Senior Verification Engineer
2 weeks ago
L&T Technology Services is seeking a highly skilled Senior DV Engineer to lead our verification efforts.
Key Responsibilities:
- Lead the development of UVM-based verification environments from scratch.
- Architect and implement Design Verification infrastructure and execute the full verification cycle.
- Verify ARM/RISC-V based CPU sub-stems or SoCs.
- Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet.
- Develop tools and flows for verification environments using E tools and scripting languages (Python, TCL, Perl, Shell).
- Experience with revision control systems like Mercurial(Hg), Git or SVN.
Requirements:
- 7+ years of experience in DV engineering.
- 8/10+ experience in StemVerilog/UVM methodology and/or C/C++ based verification.
- 8/10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies.
About Us:
L&T Technology Services is a leading global technology consulting and digital services company.
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