
Senior RTL Principal Engineer
1 week ago
Key Highlights
- Design and support of the PCIe/CXL/IDE/UALink IP solution as part of our product offerings.
Responsibilities:
- Collaborate with existing designs to add new features, ensure customer configurations are clean as part of verification regressions, and provide technical support to customers.
- Maintain design adherence to industry-standard guidelines such as LINT and CDC.
Requirements:
- Hold a degree in Electrical / Electronics / VLSI with experience in design and verification engineering, specifically RTL design.
- A minimum of 8-16 years of core RTL Design experience using Verilog is essential.
- Proficiency in System Verilog and UVM-based environment usage/debugging skills required.
- Hands-on experience in implementing complex protocols such as PCIe/CXL/IDE necessary. Prior experience in IP development teams advantageous.
- Scripting knowledge desirable for additional tasks.
Additional Requirements:
- Strong analytical and problem-solving skills.
- Ability to work independently and collaboratively as part of a team.
- Excellent communication and documentation skills.
Preferred Qualifications:
- Experience with Agile development methodologies.
- Familiarity with CI/CD tools and automation scripts.
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