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Advanced Verification Expert
3 weeks ago
Senior Design Verification Engineer
", "">We are seeking an experienced professional to lead complex verification tasks. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure.
", "">Key Responsibilities:
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- Develop and execute test plans for IP/subsystem/full-chip level verification.", "">
- Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM.", "">
- Drive functional coverage closure and ensure high-quality tape-outs.", "">
- Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios.", "">
- Participate in code reviews, debug RTL/testbench issues, and file bug reports.", "">
Required Skills and Qualifications:
", "">- ", "">
- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field.", "">
- 8+ years of experience in ASIC/SoC design verification.", "">
- Strong expertise in SystemVerilog, UVM, object-oriented programming, and assertion-based verification.", "">
- Solid understanding of digital design concepts, SoC architecture, and protocols like AMBA (AXI, AHB), PCIe, USB, or DDR.", "">
- Hands-on experience with simulation tools, waveform viewers, and version control systems (Git, Perforce).", "">
- Excellent problem-solving, communication, and team collaboration skills.", "">