Verification Engineer
2 weeks ago
Job Overview
We are seeking a highly skilled Verification Engineer to join our team.
This role is ideal for individuals who have expertise in SystemVerilog/UVM and a strong background in digital functional or mixed signal verification.
The successful candidate will have experience working with state-of-the-art tools and methodologies, including Xcelium, vManager, and Certitude.
In this position, you will be responsible for creating and maintaining verification plans, setting up verification environments, and implementing functional coverage models.
You will also be expected to elaborate, execute, and debug tests on RTL and gate levels, as well as demonstrate expertise in automotive quality expectations and project management tools such as Jira/Jama.
A minimum of 4 years of experience in the field is required for this role.
We offer a competitive compensation package and excellent benefits, including a generous notice period.
Key Responsibilities:
- Create and maintain verification plans
- Set up verification environments
- Implement functional coverage models
- Elaborate, execute, and debug tests on RTL and gate levels
- Demonstrate expertise in automotive quality expectations
- Experience with Jira/Jama project management tools
Requirements:
- 4+ years of experience in digital functional or mixed signal verification
- Expertise in SystemVerilog/UVM
- Strong background in state-of-the-art tools and methodologies
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