
Advanced Verification Specialist
2 weeks ago
We are seeking a highly skilled Senior Design Verification Engineer to join our team.
- Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
- Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
- Write and maintain directed and constrained-random test cases.
- Perform GLS (Gate-Level Simulation) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
- Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
- Validate high-speed protocols (e.g., PCIe Gen4/Gen5, USB 3.x, DDR3/4/5, LPDDR, CXL).
- Debug RTL and testbench issues using waveforms, logs, and assertions.
- Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
- Analyze functional/code/line/branch/coverage metrics and drive closure.
- Automate regressions and result analysis using scripting languages (Python, Perl, Shell, Tcl).
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- 5–15 years of experience in ASIC/IP/SoC/Processor Design Verification.
- Expertise in SystemVerilog, UVM, and constrained-random verification.
- Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
- Proven track record in any one or more of the following:
- Processor/Microarchitecture Verification (pipelines, instruction decode, coherency, etc.)
- High-speed Protocol Verification (PCIe, DDR, USB, Ethernet, CXL, etc.)
- GLS Verification (Zero-delay and SDF annotated simulations, scan chain checks, X-handling)
- Strong debugging skills and understanding of design specs and verification architecture.
- Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
- Familiar with DFT/scan concepts, low power (UPF), and assertion-based verification (SVA).
- Experience in ARM-based SoCs or RISC-V CPU verification.
- Exposure to formal verification, LEC, or static verification tools.
- Knowledge of post-silicon validation, FPGA prototyping, or emulation.
- Experience leading small teams or mentoring junior engineers.
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