
Senior Verification Specialist
2 days ago
We are seeking a highly skilled professional to fill the position of Design Verification Engineer. This role is critical in ensuring the quality and functionality of various IPs and/or SoCs.
The selected candidate will be responsible for implementing simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
In addition, this individual will assist with developing test-plans, debugging failures and analyzing coverage information.
Key Requirements:
- At least 8 years of design verification experience
- Master's degree (or higher) in Electrical Engineering/Electrical and Computer Engineering/Electronic and Communication Engineering
- Excellent knowledge of computer architecture and design verification fundamentals
- Experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
- Hands-on experience in developing complex test bench in System Verilog using OVM/UVM methodology
- Experience in Low Power Simulation/UPF setup, debug low power simulation failures
- Exposure to scripting languages like Perl, Unix shell or similar languages
- Good understanding of assembly language programming
It is essential that the candidate has hands-on experience in PCIe MAC, OR USB MAC OR Bluetooth MAC OR Wifi 802.11 MAC layer protocol.
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