Senior ASIC Verification Specialist

2 days ago


Noida, Uttar Pradesh, India beBeeVerification Full time US$ 90,000 - US$ 1,20,000
Verification Engineer

The primary role of this position is to develop and implement complex verification environments for ASIC designs.

We are seeking a skilled Verification Engineer to join our team, responsible for identifying verification environment requirements from various sources such as specifications, design functionality, and interfaces.

The ideal candidate should be able to generate verification test plans, verification environment documentation, and test environment usage documentation.

This engineer will work closely with architects, designers, and VIP teams to collaborate on the development of verification environments.

Key responsibilities include defining, developing, and verifying complex UVM verification environments, evaluating and exercising various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics (functional coverage and code coverage).

Additionally, this engineer will help identify design problems, possible corrective actions, and inconsistencies in documented functionality, improve methodologies and execution efficiency, and assist leads in mentoring junior engineers and debugging complex problems.

Knowledge of Verilog, VHDL, and/or SystemVerilog is required, while proficiency with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is highly desirable. An understanding of UVM verification methodology is essential.

This is a challenging opportunity for a skilled Verification Engineer who is passionate about delivering high-quality verification environments that meet the requirements of complex ASIC designs.



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