Senior Analog Circuit Designer

4 days ago

Jodhpur, Rajasthan, India beBeePhysicalDesign Full time ₹ 2,00,00,000 - ₹ 2,50,00,000
Lead Physical Design Engineer Opportunity

We are seeking a highly experienced and skilled Lead Physical Design Engineer to lead our advanced mixed signal chip project. The ideal candidate will have extensive experience in all phases of the IC design process, including RTL->GDS2, with a focus on analog/mixed/custom signal placement and routing.

The successful candidate will be responsible for leading the implementation of a complex mixed-signal System on Chip (SoC), building and guiding a team of implementation engineers, working with external IP vendors to integrate blocks into the design, and ensuring that each aspect of the design meets the specified requirements.

This is a unique opportunity to work on cutting-edge technologies, collaborate with top engineers and leaders worldwide, and showcase your abilities and experience from day one while learning from the world's most respected companies.

As a Lead Physical Design Engineer, you will be part of a dynamic team that invests in continuous learning and growth, providing opportunities for career development and advancement.

We are looking for a highly motivated and talented individual who can contribute to and guide the development process to meet stringent industry segment requirements. If you are eager to learn and implement groundbreaking new hardware technology, we encourage you to apply.

  • Extensive experience in all phases of the IC design process from RTL->GDS2
  • Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal SoCs
  • TSMC 7nm PNR sign-off experience using a full COT flow from RTL/gate to GDS
  • Hierarchical Place & Route experience
  • Floorplanning, clock & power network architecture and design experience
  • UPF/CPF power intent flow – multiple supply domains (bump, deca, power switch placement methods) knowledge
  • Thorough understanding of digital design, timing analysis, and DFT
  • LVS/DRC/ERC, EMIR (static & dynamic) knowledge
  • FCBGA I/O ring layout knowledge

Eager to learn & implement ground breaking new hardware technology? We welcome you to join us.

Job Requirements

Key Skills and Qualifications:

  • Strong background in physical design engineering
  • Experience with TSMC 7nm process node
  • Knowledge of hierarchical place and route tools
  • Skills in floorplanning and clock/power network architecture
  • Understanding of digital design and timing analysis
  • Proficiency in LVS, DRC, ERC, and EMIR tools

Desired Skills and Experience:

  • Experience with UPF/CPF power intent flow
  • Knowledge of FCBGA I/O ring layout
  • Background in analog/mixed/custom signal PNR
Benefits

As a member of our dynamic team, you will have access to:

  • Opportunities for career development and advancement
  • Continuous learning and growth
  • Collaboration with top engineers and leaders worldwide
  • Access to cutting-edge technologies

Join us in this exciting opportunity to shape the future of hardware technology

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