
Senior ASIC Design Engineer Position Available
5 days ago
Job Title: ASIC Engineer - Physical Design
We are seeking a skilled and experienced ASIC Physical Designer to join our team. As a key member of our design team, you will be responsible for all aspects of physical design for full-chip/block implementations, including floorplanning, placement, budgeting, clock tree planning and analysis, scan re-ordering, clock tree synthesis, placement optimizations, routing, timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, low power solution development & implementation.
The ideal candidate will have sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc.
You will work closely with the methodology team to solve implementation challenges and provide inputs to improve the physical design flow.
Key responsibilities include:
- Design automation expertise
- Timing constraints management
- SI prevention techniques
- Power reduction strategies
Must have prior experience with Synopsys/Cadence/Mentor place and route tools and completed designs in 16nm and or 7nm.
PREFERRED QUALIFICATIONS:
- Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
- Track record of taping out complex chips on advanced process nodes
Salary is negotiable based on qualifications and experience. Benefits include comprehensive health insurance, 401(k) plan, and paid time off.
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