
Senior ASIC Design Verification Specialist
9 hours ago
Develop and execute comprehensive verification strategies for complex ASIC designs. Utilize System Verilog (SV) and UVM methodologies to drive verification efficiency and effectiveness.
A successful candidate will possess strong expertise in functional, formal, GLS (Gate-Level Simulation), power, and CPU verification techniques. They will work closely with RTL designers to understand design specifications and requirements, and write and maintain C/C++ test benches for verification environments.
Key responsibilities include:
- Conducting thorough coverage analysis and driving coverage closure.
- Debugging issues found during verification and collaborating with design teams to resolve them.
- Participating in design and verification reviews to provide insights and suggestions for improvements.
Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 3 years of experience in ASIC design verification.
- Proficiency in System Verilog, UVM, and C/C++ programming languages.
- Strong knowledge of functional, formal, GLS, power, and CPU verification methodologies.
- Excellent debugging and problem-solving skills.
- Effective communication and teamwork abilities.
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